1. Field of the Invention
The present invention relates to a photoelectric conversion device used as an image pickup device of a digital camera and the like and a method of manufacturing the photoelectric conversion device. This photoelectric conversion device relates to a semiconductor device having a buried layer in part of an anode or a cathode of a photodiode, such as a CCD having a sensor structure and a CMOS sensor.
2. Related Background Art
As prior art there is a photoelectric conversion device having a buried layer in a photodiode of a CCD and a CMOS sensor.
FIG. 4 is a conceptual drawing which shows the sectional structure of a photodiode part of a conventional photoelectric conversion device. The reference numeral 401 denotes a semiconductor substrate of Si etc. (the N type, by way of example), the numeral 402 a buried layer which defines the lower part of a photodiode (the P type, by way of example), the numeral 403 an epitaxial layer (the N type, by way of example), the numeral 404 a barrier diffusion layer, which defines a transverse photosensitive region of the photodiode (the P type, by way of example), and the numeral 405 a charge-storage diffusion layer of the photodiode (the N type, by way of example).
For a photodiode structure, it is possible to consider a CCD and a CMOS sensor under the same configuration requirements. In the case of this structure, the region surrounded by the buried layer 402 and the barrier diffusion layer 404 becomes a photosensitive region of each sensor. In this structure, the spectral responsibility of a sensor is determined by the material properties of the epitaxial layer 403, the position from the surface of the buried layer 402 and the concentration distribution of impurities in the buried layer 402. When the buried layer 402 is formed from Si, in order to adapt the spectral responsibility to the visible rays of human beings, it is desirable that the peak of the impurity concentration of the buried layer 402 be at a depth of not less than 3 μm from the surface.
What should be considered in this connection is how to form this buried layer 402. Prior art includes a method by which an epitaxial layer 403 is formed after the formation of a buried layer 402, as disclosed in the Japanese Patent Application Laid-Open No. 2000-232214 (pages 5 and 6, FIG. 2) and a method by which after the formation of an epitaxial layer 403, a buried layer 402 is later formed by use of the high-energy ion implantation process, as disclosed in the Japanese Patent Application Laid Open No. H09-246514 (paragraph 0073, FIG. 2). When a buried layer is to be formed on the whole area of a substrate 401 surface, both methods have no problem. However, when a buried layer 402 is to be formed in part of a substrate 401 surface, patterning by the photolithography process etc. is necessary in the former method. In the latter method, it is necessary to use an extremely thick mask for ion implantation.
On the basis of the above-described precondition, it is thought that in a peripheral part of a sensor, a driving circuit by a MOS transistor etc. is disposed in the same substrate. Not only in a CMOS sensor naturally, but also in a CCD, it is desirable that both an NMOS and a PMOS can be disposed in a peripheral part.
On the precondition that the number of steps be not to be increased, as described above, the buried layer 402 extends over the whole area of the substrate 401. In other words, it follows that the buried layer 402 is present also in the lower part where the MOS transistor is to be disposed. By way of example, a case where the substrate 401 and the epitaxial layer 403 are of the N type and the buried layer 402 is of the P type is considered.
When both N type wells and P type wells are disposed in a peripheral circuit part, the N type wells become electrically connected via the epitaxial layer 403 and obtain the same potential. However, the P type wells are in a separated state and electrically independent, and there is a possibility that the P type wells can be individually controlled.
In order to ensure a completely electrical isolation, the formation of a structure which leads to the lower buried layer 402 is the most important problem. When the P type wells and the buried layer 402 are connected, the multiple P type wells obtain the same potential via the buried layer 402. When a peripheral circuit is built by use of a CMOS, this limits the degree of freedom of the circuit and hence this is undesirable.
If the buried layer 402 is fabricated in an area except the peripheral circuit part and not over the whole area of the substrate 401, the isolation problem of P type wells is easy as described above. In this case, however, the number of steps increases and the mask problem arises. Thus in any case, problems related to the patterning of the buried layer 402 remain.
Furthermore, even when the P type wells are not connected directly to the buried layer 402, the impurity concentration of the epitaxial layer 403 is not more than the order of 1E15 (1×1015)/cm3 at most. Therefore, it is difficult to ensure an electrical isolation of the P type wells in the parasitic bipolar structure of buried layer 402-epitaxial layer 403-P type wells.
The above-described situation applies to a case where all the conduction type are reversed.